1. Field of the Invention
This invention relates to a logic circuit of the precharge type, and more particularly to a logic circuit suitable for fabricating a large scale integrated circuit.
2. Description of the related art including information disclosed under .sctn..sctn. 1.97-1.99
In the logic circuit of this type, the output node is precharged according to a precharge signal to a predetermined potential. The potential is changed or kept according to an input signal, so that the logic circuit produces a logic "0" or logic "1" signal. A typical example of the precharge type of logic circuit is shown in FIG. 1. The logic circuit of FIG. 1 is a logic gate 11 constituting an inverter circuit. The logic circuit is made up of P channel MOS (metal oxide semiconductor) transistor Q1 and two N channel MOS transistors Q2 and Q3, and inverter INV. These transistors Q1 to Q3 are connected in series between power potential Vcc terminal and ground potential Vss terminal. The transistors Q1 and Q3 are coupled with precharge signal .phi.1 via inverter INV, to selectively set logic gate 11 in a precharge mode or in an operation mode according to precharge signal .phi.1. During a high (H) level period of precharge signal .phi.1, transistor Q1 is turned on, while transistor Q3 is turned off. The logic gate 11 is in the precharge mode, and its output terminal is at the potential approximate to power potential Vcc. During a low (L) level period, transistor Q1 is turned off, while transistor Q3 is turned on. Its output terminal is at the potential approximate to ground potential Vss.
Input latch circuit 12 is provided at the prestage of the precharge type logic gate 11. This latch circuit 12 latches the input signal at the leading edge of latch signal .phi.1 as the precharge signal .phi.1, and outputs the latched signal to logic gate 11. Output latch circuit 13 is provided at the prestage of logic gate 11. This circuit 13 latches the logic output of logic gate 11 at the trailing edge of latch signal .phi.2, and outputs the latched signal to the next stage circuit.
When a logic gate array is formed of a plurality of logic circuits arrayed on a semiconductor chip in a matrix fashion, each comprising precharge type logic gate 11, input latch circuit 12 and output latch circuit 13, the input latch circuit 12 and the output latch circuit 13 may be transparent type latch circuits as shown in FIG. 2. Such circuits are simple in construction and suitable for a high packing density of the logic gate array.
The latch circuit of the transparent type is made up of clocked inverters 21 and 22, and inverter 23. Clocked inverter 21 is driven by a clock signal .phi. to be a latch signal. Clocked inverter 22 is driven by the inverted clock signal .phi.. The latch circuit outputs the input signal during the high level period of latch signal .phi., and latches the input signal at the trailing edge of latch signal .phi..
When a two-phase clock system of non-overlap phase type is used for the FIG. 1 logic circuit, first and second clock signals .phi.1 and, having H (high) level periods that are not overlapped with each other are used as the latch signals applied to input latch circuit 12 and output latch circuit 13.
Input latch circuit 12 and output latch circuit 13 latch the input signals at the trailing edges of latch signals .phi.1 and .phi.2, respectively. When the system operation is tested, the system is stopped when first and second clock signals .phi.1 and .phi.2 are both at a "L" (low) level.
In this case, when the system is stopped during the period t1 (FIG. 3) ranging from the trailing edge of clock signal .phi.2 to the leading edge of clock signal .phi.1, input latch circuit 12 is stopped in the latched state of the input signal, and the inverted signal of the signal input to input latch circuit 12 is latched in output latch circuit 13. On the contrary, when the system is stopped during the period t2 (FIG. 3) from the trailing edge of first clock signal .phi.1 to the leading edge of second clock signal .phi.2, the logic output from precharge logic circuit 11 is not latched. The reason for this is that output latch circuit 13 has latched the previous logic output during the period t2, and thus the logic output from the precharge type logic circuit 11 is not held. Charges at the output node of logic circuit 11 leak during the inoperative state of the system.
For the above reason, in the conventional logic circuit of the precharge type, the stop/restart period is limited.